FPGA Leakage Power Reduction Using Asymmetric SRAM Cells
نویسندگان
چکیده
This report shows the leakage power and the access latency of a novel asymmetric SRAM cell [1] using HSPICE simulation under different scenarios for FPGA architecture. Then, it shows that we are able to take advantage of the features of asymmetric cells and achieve 2X leakage power reduction for LUT-based FPGA.
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تاریخ انتشار 2002